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那么这5ns是从源FPGA引脚到目标FPGA引脚测量的吗？
这表明在常规PCB走线上的距离超过3英尺。无论如何，您可以通过IDELAY将时钟延迟到第一个fpga，并且不会延迟第二个FPGA;
这可以帮助你平衡歪斜。
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以下为原文

So this 5ns is measured from the source FPGA pin to target FPGA pin? This suggests more than 3 feet separation on a regular PCB trace.

Anyway, you can delay the clock into the first fpga by IDELAY and give the second FPGA without delay; this would help you balance the skew.- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

建议：使用PCI总线方法进行时钟分配。
时钟发生器为每个人提供总线时钟的副本，包括主设备。
时钟发生器的输出（通过构造）完全相位对齐。
从发生器到每个从设备（和主设备）的传输路径被构造成相等的长度，因此PCI总线上的每个“方”接收与所有其他PCI总线“各方”相位对准的时钟。
这意味着您的FPGA充当“主”（AND作为时钟发生器）生成两个相同时间的时钟输出副本。
一个副本转到从FPGA，另一个副本返回主FPGA。
两个时钟互连构造成在长度和结构上相同，因此互连不会导致两个时钟之间的偏斜。
这有意义吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Suggestion:? use the PCI bus approach to clock distribution.? The clock generator provides a copy of the bus clock for everyone, including the master.? The clock generator's outputs are (by construction) perfectly phase aligned.? The transmission paths from the generator to each of the slaves (and masters) are constructed to be equal length, and so each 'party' on the PCI bus receives a clock which is phase aligned with all the other PCI bus 'parties'.
?
This means that your FPGA acting as 'master' (AND as clock generator) generates two identically timed output copies of the clock.? One copy goes to the slave FPGA, and the other copy is returned to the master FPGA.? The two clock interconnects are constructed to be identical in length and construction, so the interconnect does not contribute to skew between the two clocks.
?
Does this make sense?
?
-- Bob Elkind
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